Synopsys has started offering its DDR5 / DDR4 physical interface (PHY) and controller for next-generation system-on-a-chip (SoC) that will be manufactured using TSMC’s N5 (5nm) manufacturing technology. The IP package allows SoC manufacturers to add support for both types of memory on their chips configured using TSMC’s N5 node. Synopsys is the first IP company to offer a memory solution that supports both DDR4 and DDR5 with data transfer rates of up to 6400 MT / s.
Synopsys’ DesignWare IP package for DDR5 / DDR4 memory implementations is quite advanced. It includes a DDR5 / DDR4 controller with command scheduler, memory protocol manager, optional ECC, dual channel support, and DFI 5.0 interface to its PHY. The block supports 64 CAM inputs for reads, 64 CAM inputs for writes, and latencies as low as 8 clock cycles. The controller can be programmed using Arm’s AMBA 3.0 APB interface. In addition, the company offers its proven DDR5 / DDR4 physical layer on silicon (via Design & Reuse) which supports data transfer rates of up to 6400 MT / s as well as memory subsystems with up to 6,400 MT / s. ‘with four physical ranks. Obviously, the controller and PHY support all standard JEDEC capabilities of DDR4 and DDR5.
The IP package offered by Synopsys allows developers of various chips (CPU, SoC, SSD controllers, etc.) to integrate the controller IP and physical interface into their N5 design, then verify that everything is working properly there. Provided verification IP help designed by the company. .
The implementation of memory support gets more complicated with each new generation, and supporting different types of memory with a single design has always been difficult. Intel intends to support both DDR4, DDR5, and (eventually) LPDDR4 / LPDDR5 with its upcoming Alder Lake processors. However, Intel has a lot of resources and can implement both the controller and the PHY itself. Small manufacturers tend to license this intellectual property.
Synopsys started to license their DDR5 / DDR4 controller a while ago, but without a PHY its implementation was rather complicated for many small SoC designers. Now that Synopsys has its DDR5 / DDR4 physical layer (via design and reuse) available for TSMC’s N5 manufacturing technology, it will be considerably easier for SoC designers to add support for existing memory and of the next generation.
Building a memory controller that supports different types of memory is not as simple as building models that only support one memory standard. But building a physical layer that supports different DRAM technologies is trickier, as different types of memory tend to have different physical encoding sublayers (PCS) and physical media dependent (PMD) layers as well. only tensions.
Cadence has been offering controllers that have supported DDR5 and LPDDR5 and PHY for some time now, but the company has yet to roll out an IP package that enables both DDR4 and DDR5 to be implemented.